The prior art has solved some of the difficulty encountered in testing the array peripheral circuits but the difficulty in testing the logical elements and array personalization remain. With regard to the testing of peripheral circuits, for example, IBM Technical Disclosure Bulletin, Vol. 22, No. 5, page 1866 entitled "Pretesting Laserable PLA Peripheral Circuits," discloses the testing of PLA peripheral circuits prior to personalization by providing additional test lines and test transistors connected to input test points.
The difficulties encountered in testing the logical elements and the accuracy of personalization have not been adequately solved by the prior art. One prior art technique for testing array personalization is to sequentially apply every possible input bit pattern to the array and monitor the array outputs against known correct outputs. Clearly, for a large array, this procedure can be tedious and time consuming, thereby negating the quick turn-around time obtained by using an array over custom logic. For example, if the array has 16 input lines, there are over 65,000 possible input bit patterns, each of which must be tested. Such a procedure is both time consuming and costly.
Besides being costly, the prior art technique for testing array personalization is inadequate in that it may not spot all possible personalization defects. This is so because in a logic array there is not a one-to-one correspondence between digital input patterns and array output lines activated. In other words, a given digital input pattern may activate more than one output line. An output from the logic array in response to a given input bit pattern may show that an array output line has been activated, but not necessarily the correct array output line. Thus, it is sometimes impossible to detect defective personalization even if many combinations of input patterns are applied.
As an example of the inadequacies of the prior art technique, consider the testing of the PLA structure described above. In order to minimize the PLA size for generating a given logic function, the array personalization includes many "don't cares." Due to the presence of "don't cares" in the array personalization, a given input pattern will generally activate more than one PLA row. If the output columns are monitored for a given logical output in response to a given digital input, it cannot be ascertained whether this logical output is due to the activation of the proper row or is due to another row being activated by the given digital input. Due to the nature of the associative match in the PLA, it may be impossible to detect the defective personalization of a given row.